1. Field of the Invention
The present invention relates to a magnetic memory device, and more particularly to a magnetic memory device having a nonvolatile memory cell array which uses a magnetic tunnel junction as each memory cell.
2. Description of the Background Art
 less than Tunnel Magnetic Resistance Effect greater than 
A structure in which an insulative material is sandwiched between two ferromagnetic materials is termed xe2x80x9cmagnetic tunnel junction (MTJ)xe2x80x9d.
FIG. 67 shows a concept of an MTJ. In FIG. 67, an insulating layer TB is provided, being sandwiched between ferromagnetic layers FM21 and FM22 and a voltage is applied to the ferromagnetic layers FM21 and FM22.
In this structure, when a current tunneling the insulating layer TB is measured, it is observed that the measured current value varies depending on the directions of magnetization of the two ferromagnetic layers.
This phenomenon is termed xe2x80x9ctunnel magnetic resistance (TMR) effectxe2x80x9d. The TMR effect will be discussed, referring to FIGS. 68 to 70.
FIG. 68 is a schematic view showing the density of states N(E) of a transition metal. In FIG. 68, the horizontal axis indicates the density of states and the vertical axis indicates an energy E, and electrons included in atoms are grouped according to the directions of spin. Specifically, in FIG. 68, the density of states of atoms having electrons whose direction of spin is downward is shown on the left hand and that of atoms having electrons whose direction of spin is upward is shown on the right hand.
Further, in FIG. 68, since the atoms filled with electrons up to the Fermi level are schematically shown among the 3d orbit and the 4s orbit, the atoms filled with electrons up to the Fermi level are hatched with the Fermi level as the boundary.
The reason why the transition metal becomes a ferromagnetic substance is that the number of electrons whose direction of spin is downward and that of electrons whose direction of spin is upward are different on the 3d orbit among the atoms filled with electrons up to the Fermi level.
In other words, since number of electrons whose direction of spin is downward and that of electrons whose direction of spin is upward are equal on the 4s orbit, the electrons on the 4s orbit do not contribute to generation of magnetism.
FIGS. 69 and 70 are schematic views illustrating the TMR effect. In FIG. 69, among the 3d orbit of atoms constituting the ferromagnetic layer FM21 on the left side of the insulating layer TB, the density of states of atoms having the electrons of downward spin is higher than that of atoms having the electrons of upward spin and therefore the direction of magnetization is downward on the whole.
Similarly, the direction of magnetization of the ferromagnetic layer FM22 on the right side of the insulating layer TB is downward on the whole.
Tunneling of electrons mainly occurs so that the directions of spin in an initial state and a final state can be conserved. In the case of FIG. 69, since both the density of states of downward spin in the initial state (inside the ferromagnetic layer FM21) and that in the final state (inside the ferromagnetic layer FM22) are large, the tunneling probability is large and a tunneling current is also large. In other words, the tunnel magnetic resistance is small.
On the other hand, in FIG. 70, since the density of states of upward spin in the initial state (inside the ferromagnetic layer FM21) is large and that in the final state (inside the ferromagnetic layer FM22) is small, the tunneling probability is small and the tunneling current is also small. In other words, the tunnel magnetic resistance is large.
The tunnel magnetic resistance rate (TMRR) is expressed by the following equation;                     TMRR        =                                                            R                                  A                  ⁢                                      xe2x80x83                                    ⁢                  F                                            -                              R                F                                                    R              A                                =                                                    P                1                            ⁢                              P                2                                                    1              -                                                P                  1                                ⁢                                  P                  2                                                                                        (        1        )            
where the resistance in a case where the directions of magnetization of the two ferromagnetic layers are the same is RF and that in a case where those are opposite is RAF.
Further, in the above Eq. (1), P1 and P2 denotes the spin polarizabilities of the ferromagnetic layers FM21 and FM22, respectively.
Assuming that the density of states of xcfx81 spin band in the Fermi surface is D xcfx81 (EF), the spin polarizability is expressed as;                     P        =                                            D              ↑                              (                                  E                  F                                )                                      -                          D              ↓                              (                                  E                  F                                )                                                                        D              ↑                              (                                  E                  F                                )                                      +                          D              ↓                              (                                  E                  F                                )                                                                        (        2        )            
Specifically, the spin polarizability becomes larger as the difference between the density of states of upward spin and that of downward spin is larger. Further, as the spin polarizability approximates 1, the TMRR becomes larger. Furthermore, it is known that the spin polarizability and the magnetization are in proportion to each other. Herein, the spin polarizabilities of various magnetic materials are shown in Table 1:
A device utilizing the above TMR effect to store data, making correspondence between the directions of magnetization of two ferromagnetic layers and two values, 0 and 1, is an MRAM (Magnetic Random Access Memory).
Accordingly, though it is required to change the direction of magnetization of one of the two ferromagnetic layers in the MTJ, in some cases, the directions of magnetization of both ferromagnetic layers are changed in the structure of FIG. 67 when the magnetic field is given thereto. Then proposed is a structure as shown in FIG. 71, in which an antiferromagnetic layer is formed on the one of the ferromagnetic layers to fix the direction of magnetization of the one of the ferromagnetic layers.
In FIG. 71, the insulating layer TB is sandwiched between the ferromagnetic layers FM21 and FM22 and an antiferromagnetic layer AF is formed above the ferromagnetic layer FM21. Further, a positive electrode of a DC power supply is connected to the antiferromagnetic layer AF and a negative electrode thereof is connected to the ferromagnetic layer FM22.
When a ferromagnetic material and an antiferromagnetic material are formed adjacently to each other, a magnetic flux penetrating these materials is closed to fix the direction of magnetization. This structure is termed xe2x80x9cspin valve type ferromagnetic tunnel junction elementxe2x80x9d.
FIG. 72 shows a structure of variation of the spin valve type ferromagnetic tunnel junction element. In FIG. 72, the insulating layer TB is sandwiched between the ferromagnetic layers FM21 and FM22, the antiferromagnetic layer AF is formed above the ferromagnetic layer FM21 and a ferromagnetic layer FM23 is formed below the ferromagnetic layer FM22.
Herein, the antiferromagnetic layer AF is made of, e.g., IrMn containing Ir (iridium) of 20 to 30 atom. %, to fix the direction of magnetization of the ferromagnetic layer FM21, and the ferromagnetic layer FM21 is made of CoFe having large coercivity because it is better that the direction of magnetization should be hard to reverse with respect to the external magnetic field.
Further, as discussed earlier referring to Eq. (1), since the tunnel magnetic resistance rate (TMRR) becomes larger as the spin polarizability is larger, CoFe is used as a material having large spin polarizability.
On the other hand, though the ferromagnetic layer FM22 is also made of CoFe, it is desirable that the ferromagnetic layer FM22 should be made of a material having small coercivity so that its direction of magnetization may be controlled by a smaller external magnetic field.
In the structure of FIG. 72, Ni80Fe20 (permalloy) having small coercivity and small spin polarizability is used as the ferromagnetic layer FM23 to allow easy reverse in the direction of magnetization of the ferromagnetic layer FM22. The direction of magnetization of the ferromagnetic layer FM22 can be thereby reversed by a small external magnetic field.
FIG. 73 shows a practical structure of the spin valve type ferromagnetic tunnel junction element of FIG. 72, and FIG. 74 shows measured characteristics of TMR in this structure.
In FIG. 73, the insulating layer TB is formed above a layered structure consisting of the antiferromagnetic layer AF and the ferromagnetic layer FM21 which are formed two-dimensionally on a substrate BD, and the ferromagnetic layer FM23 is formed above the insulating layer TB. A measured result of change in magnetic resistance MR at the time when the external magnetic field is given to such a structure is shown in FIG. 74.
In FIG. 74, the horizontal axis indicates the magnetic field (converted by 1 oersted=about 79 A/m) and the vertical axis indicates the tunnel magnetic resistance rate (TMRR). It can be seen from FIG. 74 that the TMRR is 36%, the magnetic field required to reverse the direction of magnetization is low, i.e., about 30 (xc3x9779 A/m), and a hysteresis symmetric with respect to the direction of magnetization is achieved.
 less than Structure and Operation Principles of MRAM greater than 
In the MRAM, the directions of magnetization of the two ferromagnetic materials in the magnetic tunnel junction element making up a memory cell are controlled to be the same or opposite by the external magnetic field and the state where the directions of magnetization are the same or the state where the directions of magnetization are opposite is brought into correspondence with 0 or 1, to store data.
The stored data can be read out by passing a predetermined current through the memory cell and sensing the voltages at both ends of the tunnel magnetic resistance. Since sensing becomes easier as the tunnel magnetic resistance rate (TMMR) is larger, a ferromagnetic material having large spin polarizability is advantageous to the MRAM.
Further, in order to write data, it is only necessary to change the direction of magnetization of one of the ferromagnetic materials by using the magnetic field generated by passing a predetermined current through the lines (word line and bit line).
 less than Structure of MRAM Cell greater than 
Now, discussion will be made below on a structure and an operation of an MRAM disclosed in U.S. Pat. No. 5,793,697 as a background-art example.
FIG. 75 is a perspective view showing an MRAM cell array and cells. In FIG. 75, word lines 1, 2 and 3 are provided in parallel to one another and bit lines 4, 5 and 6 are provided in parallel to one another, intersecting the word lines thereabove.
MRAM cells (hereinafter, sometimes referred to simply as xe2x80x9ccellxe2x80x9d) 9 are formed at intersections of the word lines and the bit lines therebetween. In FIG. 75, as shown in an enlarged view, the MRAM cell 9 has a structure in which a silicon pn-junction diode 7 and a magnetic tunnel junction element (MTJ) 8 are layered on the word lines.
FIG. 76 is a schematic view showing a cross-sectional structure of the MRAM cell 9. Further, FIG. 76 shows the MRAM cell 9 on the word line 3, where the word line 3 is provided on a silicon substrate 80 and thereon an n+ silicon layer 10 and a p+ silicon layer 11 are layered to make up the pn-junction diode 7. The pn-junction diode 7 is covered with an insulating film such as a silicon oxide film 13.
A tungsten stud 12 is formed above the pn-junction diode 7 and the pn-junction diode 7 is electrically connected to the MTJ 8 through the tungsten stud 12. Further, the silicon oxide film 13 is so provided as to also cover the tungsten stud 12 and surfaces of the tungsten stud 12 and the silicon oxide film 13 are planarized by CMP (Chemical Mechanical Polishing).
MTJ 8 has a layered structure consisting of a template layer 15 (having a film thickness of 10 nm) made of platinum (Pt), an initial ferromagnetic layer 16 (having a film thickness of 4 nm) made of permalloy of Ni81Fe19, a diamagnetic layer 18 (having a film thickness of 10 nm) made of Mn54Fe46, a ferromagnetic layer 20 (having a film thickness of 8 nm) made of permalloy of CoFe or Ni81Fe19 and having a fixed direction of magnetization, a tunnel barrier layer 22 made of Al2O3, a soft ferromagnetic layer 24 made of a multilayer film consisting of CoFe having a film thickness of 2 nm and Ni81Fe19 having a film thickness of 20 nm, and a contact layer 25 made of Pt from the bottom.
Further, the tunnel barrier layer 22 is formed by depositing Al having a film thickness of 1 to 2 nm and performing the plasma oxidation method for 60 to 240 seconds with the power density of 25 W/cm2 under the oxygen pressure of 100 mTorr (100xc3x9710xe2x88x923xc3x971.33xc3x97102Pa).
Furthermore, not shown in FIG. 76, a large MTJ is actually formed entirely over a surface of the silicon oxide film 13 on the substrate 80 and the MTJ is patterned by argon ion milling with a photoresist mask, to form a plurality of small MTJs 8 as shown in FIG. 76. Each MTJ 8 is covered with a silicon oxide film 26. Further, not shown in FIG. 76, the contact layer 25 is connected to the bit lines.
The magnetic tunnel resistance of the MTJ 8 varies depending on whether the direction of magnetization of the soft ferromagnetic layer 24 discussed above is the same as that of the ferromagnetic layer 20 or opposite to. The direction of magnetization of the soft ferromagnetic layer 24 can be changed by a magnetic field generated by a current flowing the bit lines and the word lines.
Further, the magnetic tunnel resistance of the MTJ 8 greatly depends on the film thickness and the barrier height of the tunnel barrier layer 22 and the material characteristics of a film, such as roughness, at an interface below the junction.
The soft ferromagnetic layer 24 is so formed as to have an easy axis which is a direction of easy magnetization. There are two directions of magnetization along the easy axis, corresponding to two data of the memory cell, 0 and 1, respectively.
On the other hand, the ferromagnetic layer 20 is formed so that its direction of magnetization should be the same as the easy axis of the soft ferromagnetic layer 24 and the direction should not be changed depending on the operating state of the MRAM.
Such a direction of magnetization is termed xe2x80x9cunidirectional anisotropy directionxe2x80x9d. The easy axis of the soft ferromagnetic layer 24 is defined by a combination of the intrinsic anisotropy, the stress induced anisotropy and an anisotropy which depends on shape of the MTJ 8.
The intrinsic anisotropy refers to an anisotropy of magnetization intrinsic to a ferromagnetic substance, and the stress induced anisotropy refers to an anisotropy of magnetization generated at the time when a stress is applied to a ferromagnetic substance.
Further, as shown in FIG. 75, the MTJ 8 has a rectangular shape with a long side L and a short side W in a plan view. This is because the easy axis of the soft ferromagnetic layer 24 is defined by using the anisotropy which depends on the shape of the MTJ 8.
Next discussion will be made on a method of setting the unidirectional anisotropy direction of the ferromagnetic layer 20. The initial ferromagnetic layer 16 deposited on the template layer 15 grows with a surface ({111} surface) whose crystal orientation is a {111} orientation upward. Further, the diamagnetic layer 18 made of MnFe is deposited on the initial ferromagnetic layer 16.
These magnetic layers are deposited under the magnetic field whose direction is the same as that of the easy axis of the soft ferromagnetic layer 24 which is deposited later, and the unidirectional anisotropy direction of the soft ferromagnetic layer 24 is thereby defined.
Further, since the magnetic flux is closed between the ferromagnetic layer 20 and the diamagnetic layer 18, the direction of magnetization of the ferromagnetic layer 20 becomes harder to change by the external magnetic field than that of the soft ferromagnetic layer 24, and the direction of magnetization of the ferromagnetic layer 20 is fixed within a range of magnitude of the magnetic field generated by the current flowing the word lines and the bit lines. Moreover, since the MTJ 8 has a rectangular shape in a plan view, a magnetizing anisotropy which depends on the shape of the ferromagnetic layer 20 is generated, which contributes to the stabilization in the direction of magnetization of the ferromagnetic layer 20.
 less than Outline of Writing/Reading Operation of MRAM greater than 
Discussion will be made below on writing/reading operation of the MRAM.
When a predetermined current is passed through a word line and a bit line for address selection (referred to as xe2x80x9cselected word linexe2x80x9d and xe2x80x9cselected bit linexe2x80x9d), magnetic fields are generated around the lines and a coupled magnetic field obtained by coupling these magnetic fields is generated at an intersection (selected address) of these lines. When this magnetic field is given, the direction of magnetization of the soft ferromagnetic layer 24 in the MTJ 8 provided at the intersection of these lines is rotated in a surface of the layer, to write data.
The magnitude of the magnetic field is so designed as to be larger than that of a switching magnetic field (the magnetic field at which the direction of magnetization starts rotating) of the soft ferromagnetic layer 24, which mainly depends on the coercivity and the magnetizing anisotropy of the soft ferromagnetic layer 24.
Further, the magnetic fields generated around the selected word line and the selected bit line must be designed enough small to avoid rotation of the unidirectional anisotropy direction of the ferromagnetic layer 20. This is intended not to change the direction of magnetization of a half-selected cell. The half-selected cell refers to a cell in which the current flows in only one of the word line and the bit line which are provided thereabove and therebelow.
Thus, the architecture of the memory cell array is so designed as to avoid direct flow of the writing current into the MTJ 8, for the purpose of cutting the power consumption in data writing.
Further, the data written into the MRAM cell 9 are read out by sensing the current flowing vertically through the pn-junction diode 7 and the MTJ 8. Furthermore, since a tunneling current flows vertically through the MRAM cell 9 during operation, the occupied area of the MRAM cell 9 can be reduced.
The resistance of the tunnel barrier layer 22 made of Al2O3 in the MTJ 8 varies almost exponentially with respect to the film thickness thereof. Specifically, the current flowing in the tunnel barrier is reduced as the film thickness becomes thicker and only a current tunneling the junction flows vertically with respect to the junction.
The data in the MRAM cell 9 are read out by monitoring a voltage of the MRAM cell 9 generated when a sense current too much smaller than the writing current flows vertically in the MTJ 8.
As discussed earlier, the tunneling probability of the MTJ 8 increases as the density of states of the spin having the same polarity as the spin in the soft ferromagnetic layer 24 in the initial state is higher in the ferromagnetic layer 20 in the final state.
Accordingly, the magnetic tunnel resistance of the MTJ 8 is low when the states of spin of the soft ferromagnetic layer 24 and the ferromagnetic layer 20 are the same, in other words, the directions of magnetization of these layers are the same and is high when the directions of magnetization of these layers are opposite. Therefore, the data in the MRAM cell 9 can be read out only by monitoring the resistance of the MTJ with a microcurrent.
Further, the magnetic field generated by the sense current is negligible, which has no effect on the state of magnetization of the MRAM cell 9. Furthermore, since lines required for the reading/writing operation of the MRAM cell 9 are only the bit lines and the word lines shown in FIG. 75, an efficient memory cell array can be achieved.
 less than Writing Operation greater than 
Further discussion will be made below on the writing operation of the MRAM, referring to FIGS. 77 and 78.
FIG. 77 is an equivalent circuit diagram of the MRAM cell array of FIG. 75, where both ends of the word lines 1 to 3 are connected to a word-line control circuit 53 and both ends of the bit lines 4 to 6 are connected to a bit-line control circuit 51. Further, for convenience of illustration in FIG. 78, the word lines 1 to 3 are represented as word lines WL1 to WL3 and the bit lines 4 to 6 are represented as bit lines BL4 to BL6 in some cases.
At the intersections of the word lines 1 to 3 and the bit lines 4 to 6 provided are the MTJs 8 represented by resistance symbols and the pn-junction diodes 7 represented by diode symbols.
Herein, assuming that the word line 1 and the bit line 4 are selected, an MRAM cell 9a located at the intersection of these lines is selected.
Writing to the selected MRAM cell 9a is performed by the coupled magnetic field generated by a current IB flowing in the bit line 4 and a current IW flowing in the word line 1.
A magnetic field generated by either one of the current IB and the current IW in the cell region is smaller than that required to change the direction of magnetization of the soft ferromagnetic layer 24 in the MTJ 8.
Therefore, in the MRAM cell arrays 9b to 9e which are half-selected cells (cells in which only one of the current IB and the current IW flows in the bit lines or the word lines), no writing operation is performed.
When the magnetic fields generated by the current IB and the current IW are coupled, however, the magnitude of the coupled magnetic field becomes enough large to change the direction of magnetization of the soft ferromagnetic layer 24 in the selected memory cell 9a. 
Further, at least one of the current IB and the current IW is so designed as to flow bidirectionally in order to allow the direction of magnetization of the soft ferromagnetic layer 24 in the cell 9a to be two opposite ones. Furthermore, in FIG. 77, since two bit-line control circuits 51 and two word-line control circuits 53 are provided in pairs, both the currents IB and IW can change the directions of current flow.
FIG. 78 is a timing chart showing voltages and currents of the bit lines 4 to 6 (bit lines BL4 to BL6) and the word lines 1 to 3 (word lines WL1 to WL3).
As shown in FIG. 78, the voltages of the bit lines BL4 to BL6 in writing are set to a voltage Vb which is suitable for bidirectional currents. The voltages of the word lines WL1 to WL3 are set to a voltage Vw which is larger than the voltage Vb and positive.
On standby, these voltages are so set as to apply a reverse bias to the pn-junction diodes 7 in all the cells 9. Accordingly, neither the current IB nor the current IW flows in the memory cells on standby.
 less than Reading Operation greater than 
Next discussion will be made on a reading operation of the MRAM in more detail, referring to FIGS. 77 and 78. As shown in FIG. 78, the voltage of the word line WL1 is lowered from Vw to Vb and the voltage of the bit line BL4 is raised from Vb to Vw, to apply a forward bias to the pn-junction diode 7 in the selected cell 9a. 
In reading, the voltages of non-selected bit lines 5 and 6 are still the standby voltage Vb and those of the non-selected word lines 2 and 3 are still the standby voltage Vw.
Further, since there is no voltage drop from the word lines to the bit lines (in other words, 0 V is applied to the pn-junction diodes 7) in the half-selected cells 9b to 9e, no current flows in the cells.
The magnitude of a sense current 30 (see FIG. 77) flowing through the bit line BL4 and the cell 9a into the word line WL1 depends on the magnetic tunnel resistance of the selected cell 9a. In a sense circuit which is a constituent element of the bit-line control circuit 51, assuming that an average value of two current values estimated correspondingly to two states of the cell is defined as a reference current, the sense current is compared with the reference current. Then, the difference between the sense current and the reference current is amplified, to read data stored in the selected cell 9a. 
Further, as shown by the waveform of the sense current 30 in FIG. 77, the sense current 30 has two kinds of current waveforms corresponding to two magnetic states of the MTJ 8.
After reading data, the voltages of the bit line BL4 and the word line WL1 are returned to the respective standby voltages, but the magnetic state of the memory cell 9a remains after the reading operation.
As discussed above, in writing data into the MRAM cell, the magnetic fields are generated by passing a current through the bit line and the word line. Since a magnetic field larger than the switching magnetic field of the soft ferromagnetic layer which is a constituent element of the cell has to be applied to the memory cell at the selected address, a relative large current is needed to flow. For this reason, the power consumption in writing disadvantageously becomes large.
Further, the background-art MRAM cell array has a problem that it takes long period of time to perform a batch erasing or a batch writing of data in a unit of memory block constituted of at least one memory cell array.
The present invention is directed to a magnetic memory device. According to a first aspect of the present invention, the magnetic memory device comprises a plurality of bit lines and a plurality of word lines, intersecting one another without being in contact to make up a matrix; a plurality of memory cells provided at intersections of the plurality of bit lines and the plurality of word lines, including at least one magnetic tunnel junction; a plurality of first switching means connected to first ends of the plurality of bit lines, being capable of switching the electrical connection between the first ends and a first power supply or a second power supply; and a plurality of second switching means connected to second ends of the plurality of bit lines, being capable of switching the electrical connection between the second ends and the first power supply or the second power supply.
According to a second aspect of the present invention, in the magnetic memory device of the first aspect, the first switching means have first MOS transistors and second MOS transistors of the same conductivity type whose first main electrodes connected to the first ends of the plurality of bit lines, respectively, and second main electrodes connected to the first power supply and the second power supply, respectively, and the second switching means have third MOS transistors and fourth MOS transistors of the same conductivity type whose first main electrodes connected to the second ends of the plurality of bit lines, respectively, and second main electrodes connected to the first power supply and the second power supply, respectively.
According to a third aspect of the present invention, in the magnetic memory device of the first aspect, the first switching means have first MOS transistors and second MOS transistors of different conductivity types whose first main electrodes connected to the first ends of the plurality of bit lines, respectively, and second main electrodes connected to the first power supply and the second power supply, respectively, and the second switching means have third MOS transistors and fourth MOS transistors of different conductivity types whose first main electrodes connected to the second ends of the plurality of bit lines, respectively, and second main electrodes connected to the first power supply and the second power supply, respectively.
According to a fourth aspect of the present invention, in the magnetic memory device of the third aspect further comprises: fifth MOS transistors connected between the first main electrodes of the first and second MOS transistors, having the same conductivity type as that of the second MOS transistors; and sixth MOS transistors connected between the first main electrodes of the third and fourth MOS transistors, having the same conductivity type as that of the fourth MOS transistors, and in the magnetic memory device of the fourth aspect, control electrodes of the fifth and sixth MOS transistors are connected to a third power supply supplying a predetermined voltage which always brings an ON state.
According to a fifth aspect of the present invention, the magnetic memory device comprises: a plurality of memory cell arrays consisting of a plurality of bit lines and a plurality of word lines, intersecting one another without being in contact to make up a matrix, and a plurality of memory cells provided at intersections of the plurality of bit lines and the plurality of word lines, including at least one magnetic tunnel junction; and at least one memory cell array group having a plurality of main word lines provided across the plurality of memory cell arrays, and a plurality of memory cell array selecting lines provided correspondingly to the plurality of memory cell arrays, and in the magnetic memory device of the fifth aspect, the plurality of word lines are connected to outputs of first combined logic gates which are provided at intersections of the plurality of main word lines and the plurality of memory cell array selecting lines, respectively, and inputs of the first combined logic gates are connected to one of the plurality of main word lines and one of the plurality of memory cell array selecting lines which intersect each other.
According to a sixth aspect of the present invention, in the magnetic memory device of the fifth aspect, the at least one memory cell array group includes a plurality of memory cell array groups, the magnetic memory device further comprises: a plurality of global word lines provided across the plurality of memory cell array groups; and a plurality of memory cell array group selecting lines provided correspondingly to the plurality of memory cell array groups, in the magnetic memory device of the sixth aspect, the plurality of main word lines are connected to outputs of second combined logic gates which are provided at intersections of the plurality of global word lines and the plurality of memory cell array group selecting lines, respectively, and inputs of the second combined logic gates are connected to one of the plurality of global word lines and one of the plurality of memory cell array group selecting lines which intersect each other.
According to a seventh aspect of the present invention, the magnetic memory device comprises: a plurality of memory cell arrays consisting of a plurality of bit lines and a plurality of word lines, intersecting one another without being in contact to make up a matrix, and a plurality of memory cells provided at intersections of the plurality of bit lines and the plurality of word lines, including at least one magnetic tunnel junction; and at least one memory cell array group having a plurality of main bit lines provided across the plurality of memory cell arrays, and a plurality of memory cell array selecting lines provided correspondingly to the plurality of memory cell arrays, and in the magnetic memory device of the seventh aspect, the plurality of bit lines are connected to outputs of first combined logic gates which are provided at intersections of the plurality of main bit lines and the plurality of memory cell array selecting lines, respectively, and inputs of the first combined logic gates are connected to one of the plurality of main bit lines and one of the plurality of memory cell array selecting lines which intersect each other.
According to an eighth aspect of the present invention, in the magnetic memory device of the seventh aspect, the at least one memory cell array group includes a plurality of memory cell array groups, the magnetic memory device further comprises: a plurality of global bit lines provided across the plurality of memory cell array groups; and a plurality of memory cell array group selecting lines provided correspondingly to the plurality of memory cell array groups, and in the magnetic memory device of the eighth aspect, the plurality of main bit lines are connected to outputs of second combined logic gates which are provided at intersections of the plurality of global bit lines and the plurality of memory cell array group selecting lines, respectively, and inputs of the second combined logic gates are connected to one of the plurality of global bit lines and one of the plurality of memory cell array group selecting lines which intersect each other.
According to a ninth aspect of the present invention, the magnetic memory device comprises: a memory cell array consisting of a plurality of bit lines and a plurality of word lines, intersecting one another without being in contact to make up a matrix, and a plurality of memory cells provided at intersections of the plurality of bit lines and the plurality of word lines, including at least one magnetic tunnel junction; and an inductor, and in the magnetic memory device of the ninth aspect, the at least one magnetic tunnel junction has a soft ferromagnetic layer whose direction of magnetization is changeable, and the inductor generates a magnetic field along an easy axis which is a direction for easy magnetization of the soft ferromagnetic layer.
According to a tenth aspect of the present invention, in the magnetic memory device of the ninth aspect, the at least one magnetic tunnel junction is provided so that the easy axis coincides with a direction of extension of the plurality of bit lines or the plurality of word lines, and the inductor has a coil-like shape, being so provided along the direction of extension of the plurality of bit lines or the plurality of word lines which coincides with the easy axis, as to surround the memory cell array.
According to an eleventh aspect of the present invention, the magnetic memory device comprises: at least one memory cell array consisting of a plurality of bit lines and a plurality of word lines, intersecting one another without being in contact to make up a matrix, and a plurality of memory cells provided at intersections of the plurality of bit lines and the plurality of word lines, including at least one magnetic tunnel junction; and at least one flash bit line and at least one flash word line both having a flat-plate shape, being so provided outside the plurality of bit lines and the plurality of word lines in the at least one memory cell array, as to cover a formation region of the plurality of bit lines and the plurality of word lines.
According to a twelfth aspect of the present invention, in the magnetic memory device of the eleventh aspect, the at least one memory cell array includes a plurality of memory cell arrays, the plurality of memory cell arrays are provided in matrix, the at least one flash bit line and at least one flash word line include a plurality of flash bit lines and a plurality of flash word lines, respectively, which are provided in matrix along the arrangement of the plurality of memory cell arrays.
According to a thirteenth aspect of the present invention, the magnetic memory device comprises: at least one semiconductor chip; a shield body made of conductive material, for containing the at least one semiconductor chip; a package made of resin, for containing the shield body; a bottom-surface substrate for closing an opening of the package to seal the package; a signal transmitting bump provided in an outer main surface of the bottom-surface substrate, for transmitting a signal between the at least one semiconductor chip and the outside; and a shielding bump so provided as to surround the signal transmitting bump, being electrically connected to the shield body, and in the magnetic memory device of the thirteenth aspect, the at least one semiconductor chip includes a magnetic memory chip comprising a memory cell array which has a plurality of memory cells including at least one magnetic tunnel junction.
According to a fourteenth aspect of the present invention, the magnetic memory device of the thirteenth aspect further comprises: a first stress relieving film provided inside and outside an opening edge of the shield body; and a second stress relieving film provided on an inner wall of the shield body.
According to a fifteenth aspect of the present invention, in the magnetic memory device of the fourteenth aspect, the at least one semiconductor chip further includes a circuit chip including peripheral circuits of the memory cell array, and the magnetic memory chip and the circuit chip are contained in the shield body, being vertically layered.
According to a sixteenth aspect of the present invention, in the magnetic memory device of the thirteenth aspect, the at least one magnetic tunnel junction has a soft ferromagnetic layer whose direction of magnetization is changeable, and the shield body is made of ferromagnetic material having magnetic permeability equal to or higher than that of the soft ferromagnetic layer.
According to a seventeenth aspect of the present invention, in the magnetic memory device of the thirteenth aspect, the shield body is made of antiferromagnetic material.
According to an eighteenth aspect of the present invention, in the magnetic memory device of the thirteenth aspect, the shield body is made of multilayer film consisting of ferromagnetic material and antiferromagnetic material.
According to a nineteenth aspect of the present invention, the magnetic memory device comprises: a plurality of bit lines and a plurality of word lines, intersecting one another without being in contact to make up a matrix; and a plurality of memory cells provided at intersections of the plurality of bit lines and the plurality of word lines, including at least one magnetic tunnel junction, and in the magnetic memory device of the nineteenth aspect, the plurality of memory cells are each provided between one of the plurality of bit lines and one of the plurality of word lines, the at least one magnetic tunnel junction has a soft ferromagnetic layer whose direction of magnetization is changeable, and the at least one magnetic tunnel junction is provided so that an easy axis which is a direction for easy magnetization of the soft ferromagnetic layer has an angle of 40 to 50 degrees with respect to the direction of extension of the plurality of bit lines and the plurality of word lines.
According to a twentieth aspect of the present invention, in the magnetic memory device of the nineteenth aspect, the magnetic tunnel junction has a rectangular shape in a plan view, whose side parallel to the easy axis is longer than a side perpendicular to the easy axis.
According to a twenty-first aspect of the present invention, the magnetic memory device comprises: a memory cell array consisting of a plurality of bit lines and a plurality of word lines, intersecting one another without being in contact to make up a matrix, and a plurality of memory cells provided at intersections of the plurality of bit lines and the plurality of word lines, including at least one magnetic tunnel junction; and at least one inductor and at least one capacitor provided at two ends, respectively, of at least one of the plurality of bit lines and the plurality of word lines, for conserving a current flowing in at least one of selected bit line and selected word line by LC resonant.
According to a twenty-second aspect of the present invention, in the magnetic memory device of the twenty-first aspect, the at least one inductor includes a plurality of inductors and the at least one capacitor includes a plurality of capacitors, the plurality of bit lines includes a plurality of bit line pairs of two bit lines, the plurality of inductors includes a plurality of first inductors so provided correspondingly to the plurality of bit line pairs, as to be electrically connected between the two bit lines, and the plurality of capacitors includes a plurality of first capacitors so provided at an end opposite to the end at which the plurality of inductors are provided, as to be electrically connected to the plurality of bit lines, respectively.
According to a twenty-third aspect of the present invention, in the magnetic memory device of the twenty-second aspect, the plurality of word lines includes a plurality of word line pairs of two word lines, the plurality of inductors includes a plurality of second inductors so provided correspondingly to the plurality of word line pairs, as to be electrically connected between the two word lines, and the plurality of capacitors includes a plurality of second capacitors so provided at an end opposite to the end at which the plurality of inductors are provided, as to be electrically connected to the plurality of word lines, respectively.
The present invention is also directed to a magnetic substrate. According to a twenty-fourth aspect of the present invention, the magnetic substrate at least has a multilayer film provided entirely on a main surface thereof, for making up at least one magnetic tunnel junction.
According to a twenty-fifth aspect of the present invention, in the magnetic substrate of the twenty-fourth, the multilayer film includes an antiferromagnetic layer, a ferromagnetic layer, a tunnel barrier layer made of insulative material and a soft ferromagnetic layer provided in this order as at least one magnetic tunnel junction.
According to a twenty-sixth aspect of the present invention, in the magnetic substrate of the twenty-fifth aspect, the multilayer film further includes a two-layered film consisting of a first conductivity type impurity layer and a second conductivity type impurity layer provided below the at least one magnetic tunnel junction, constituting a pn junction.
According to a twenty-seventh aspect of the present invention, in the magnetic substrate of the twenty-fourth aspect, the multilayer film is provided on a SOI substrate, the SOI substrate comprising: a substrate portion as a base; a buried oxide film provided on the substrate portion; and a SOI layer provided on the buried oxide film.
In the magnetic memory device of the first aspect of the present invention, since the first and second switching means allow the first and second ends of the bit line to be selectively connected to the first and second power supplies, it is possible to pass bidirectional currents through the bit line, changing the direction of magnetization of the magnetic tunnel junction, to allow writing and erasing of the data
In the magnetic memory device of the second aspect of the present invention, since the first and second switching means are constituted of the first to fourth MOS transistors of the same conductivity type, the manufacturing process becomes simple.
In the magnetic memory device of the third aspect of the present invention, since the first switching means is constituted of the first and second MOS transistors of different conductivity types and the second switching means is constituted of the third and fourth MOS transistors of different conductivity types, it is possible to eliminate the necessity of applying a voltage not lower than the power supply voltage to the control electrodes of one of the first and second MOS transistors and one of the third and fourth MOS transistors in an ON state and therefore the load on the gate insulating film becomes smaller.
In the magnetic memory device of the fourth aspect of the present invention, since the fifth and sixth MOS transistors which are always in the ON state are provided between the first main electrodes of the first and second MOS transistors and between the first main electrodes of the third and fourth first MOS transistors, the stress voltage on the first main electrode of one of the first and second MOS transistors and the stress voltage on the first main electrode of one of the third and fourth MOS transistors are reduced, and the leak current caused by the stress voltages can be reduced, to thereby cut the power consumption.
In the magnetic memory device of the fifth aspect of the present invention, in a case of the magnetic memory device having a plurality of memory cell arrays, since a plurality of main word lines across a plurality of memory cell arrays and a word line across a single memory cell array are used to reduce the number of memory cells connected directly to one line, the capacitance of load can be reduced. As a result, the delay time caused by the capacitance of load becomes shorter and a high-speed access can be thereby achieved.
In the magnetic memory device of the sixth aspect of the present invention, in a case of the magnetic memory device comprising a plurality of memory cell array groups each having a plurality of memory cell arrays, since a word line across a single memory cell array, a plurality of main word lines across a plurality of memory cell arrays and a plurality of global word lines across a plurality of memory cell array groups are used to reduce the number of memory cells connected directly to one line, the capacitance of load can be reduced. As a result, the delay time caused by the capacitance of load becomes shorter and a high-speed access can be thereby achieved.
In the magnetic memory device of the seventh aspect of the present invention, in a case of the magnetic memory device having a plurality of memory cell arrays, since a plurality of main bit lines across a plurality of memory cell arrays and a bit line across a single memory cell array are used to reduce the number of memory cells connected directly to one line, the capacitance of load can be reduced. As a result, the delay time caused by the capacitance of load becomes shorter and a high-speed access can be thereby achieved.
In the magnetic memory device of the eighth aspect of the present invention, in a case of the magnetic memory device comprising a plurality of memory cell array groups each having a plurality of memory cell arrays, since a bit line across a single memory cell array, a plurality of main bit lines across a plurality of memory cell arrays and a plurality of global bit lines across a plurality of memory cell array groups are used to reduce the number of memory cells connected directly to one line, the capacitance of load can be reduced. As a result, the delay time caused by the capacitance of load becomes shorter and a high-speed access can be thereby achieved.
Since the magnetic memory device of the ninth aspect of the present invention comprises the inductor which generates a magnetic field in a direction along the easy axis which is a direction for easy magnetization of the soft ferromagnetic layer, the batch erasing or batch writing of data in a plurality of memory cells each having at least one magnetic tunnel junction can be achieved, thereby allowing a short-time processing.
In the magnetic memory device of the tenth aspect of the present invention, since the magnetic field can be efficiently generated by the coil-shaped inductor, the power supply can be cut in batch erasing or batch writing of data in a plurality of memory cells.
In the magnetic memory device of the eleventh aspect of the present invention, since the flash bit line and the flash word line are provided outside a plurality of bit lines and a plurality of word lines in at least one memory cell array and the batch erasing or batch writing of data in a plurality of memory cells each having at least one magnetic tunnel junction can be performed by passing a current through the flash bit line and the flash word line in a predetermined direction, a short-time processing can be achieved.
In the magnetic memory device of the twelfth aspect of the present invention, in a case of the magnetic memory device comprising a plurality of memory cell arrays provided in matrix, since the flash bit line and the flash word line are so provided along the arrangement of a plurality of memory cell arrays as to make up a matrix and the batch erasing or batch writing of data in a plurality of memory cells can be thereby performed, a short-time processing can be achieved.
In the magnetic memory device of the thirteenth aspect of the present invention, since at least one semiconductor chip is contained in the shield body made of conductive material, it becomes possible, in a plurality of memory cells including at least one magnetic tunnel junction, to prevent reverse of the direction of magnetization of the magnetic tunnel junction by the external magnetic field, which causes rewriting of data.
In the magnetic memory device of the fourteenth aspect of the present invention, since the first and second stress relieving films hold at least one semiconductor chip, it is possible to reduce application of an external stress on a plurality of semiconductor chips.
In the magnetic memory device of the fifteenth aspect of the present invention, since two kinds of chips, the magnetic memory chip and the circuit chip including peripheral circuits of the memory cell array, are provided, these chips are separately manufactured, thereby eliminating the necessity for considering the difference in formation temperature and allowing optimization of the respective formation temperatures. Further, the manufacturing processes proceed in parallel, thereby cutting the manufacturing time.
In the magnetic memory device of the sixteenth aspect of the present invention, since the shield body is made of ferromagnetic material having magnetic permeability equal to or higher than that of the soft ferromagnetic layer, it is possible to effectively block off the external magnetic field.
In the magnetic memory device of the seventeenth aspect of the present invention, since the shield body is made of antiferromagnetic material, it is possible to effectively block off the external magnetic field.
In the magnetic memory device of the eighteenth aspect of the present invention, since the shield body is made of multilayer film consisting of the ferromagnetic material and the antiferromagnetic material, it is possible to effectively block off the external magnetic field.
In the magnetic memory device of the nineteenth aspect of the present invention, since at least one magnetic tunnel junction is provided so that the easy axis which is a direction for easy magnetization of the soft ferromagnetic layer may have an angle of 40 to 45 degrees with respect to the direction of extension of a plurality of bit lines and a plurality of word lines, the direction of magnetization of the soft ferromagnetic layer can be surely reversed with a small amount of writing current and the power consumption in a writing operation can be thereby reduced.
In the magnetic memory device of the twentieth aspect of the present invention, since the magnetic tunnel junction has a rectangular shape whose side parallel to the easy axis is longer than the side perpendicular to the easy axis in the plan view, it becomes easy to define the easy axis by the anisotropy which depends on the shape and it becomes possible to prevent a change of easy axis.
Since the magnetic memory device of the twenty-first aspect of the present invention comprises at least one inductor and at least one capacitor for conserving a current flowing in at least one of the selected bit line and the selected word line by LC resonant, the writing current can be recycled and the power consumption in a writing operation can be thereby cut.
In the magnetic memory device of the twenty-second aspect of the present invention, a specific structure to recycle the writing current in the bit line can be obtained.
In the magnetic memory device of the twenty-third aspect of the present invention, a specific structure to recycle the writing current in the word line can be obtained.
Since the magnetic substrate of the twenty-fourth aspect of the present invention at least has the multilayer film provided entirely on a main surface thereof to make up at least one magnetic tunnel junction, in manufacturing the magnetic memory device comprising the memory cells having at least one magnetic tunnel junction, the manufacturing process can be omitted and the manufacturing cost can be cut as compared with a case where a simple semiconductor substrate is prepared and the multilayer film is formed on a main surface thereof.
In the twenty-fifth aspect of the present invention, it is possible to obtain a magnetic substrate suitable to manufacture the magnetic memory device comprising a memory cell having a single magnetic tunnel junction.
In the twenty-sixth aspect of the present invention, it is possible to obtain a semiconductor substrate suitable to manufacture the magnetic memory device comprising a memory cell having a pn-junction diode below the single magnetic tunnel junction.
In the magnetic substrate of the twenty-seventh aspect of the present invention, since at least one magnetic tunnel junction is formed on the SOI substrate which reduces parasitic capacitance of a MOSFET, the operation speed of the MOSFET becomes high and consequently that of the magnetic memory device can becomes high.
A first object of the present invention is to provide an MRAM capable of cutting power consumption in writing.
A second object of the present invention is to provide an MRAM capable of cutting time required for erasing and writing operations.
These and other objects, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.